The present invention relates generally to power electronics and, more particularly, to power factor correction (PFC) control circuits.
The average power obtained from an AC line supply through an AC-to-DC power supply is always less than the product of the RMS (root mean square) voltage and the RMS current. The ratio of the average power to the product of the RMS voltage and the RMS current is known as the power factor. For example, a converter having a power factor of 70% means that the power drawn from the line supply is 70% of the product of the voltage and current in the line and, thus, only 70% of what could be obtained with a unity power factor.
To increase the power factor of a power supply, and hence the efficiency of the power supply, it is known to employ power factor correction (PFC). One known method for achieving PFC is to force the average input current to follow an appropriately scaled instantaneous input voltage waveform. FIG. 1 is a diagram of a conventional PFC AC-to-DC power supply 10 having a rectifier bridge 12, a boost converter 14 and an analog PFC controller 16. The analog PFC controller 16, using analog circuitry, compares the output voltage (Vout) of the converter 10 to a voltage reference 8 to produce a voltage compensation signal B (Vcomp). The voltage compensation signal is multiplied by the input voltage (Vin) and divided by the square of the RMS of the input voltage. The result of this operation is compared to the input current (Iin) to determine the duty cycle of the main power switch 18 of the boost converter 14.
Although it is known to use microcontrollers for some control and monitoring functions in PFC converters, pulse-by-pulse switch control is ordinarily realized with a specialized analog pwm controller. This approach, however, limits the scope and performance of feasible control and monitoring functions. With the progress of digital technology, however, there is an increasing incentive to use digital means for the entirety of the control and monitoring functions. The speed and resolution required for such control, however, made it, until recently, prohibitively expensive to realize in low and medium power converters.
In that connection, digital signal processors (DSPs) are well suited for the task of performing all of the control functions for a PFC converter. DSPs can implement pulse-by-pulse switch control by executing firmware algorithms that calculate the optimal on-time duration of the main power switch. At the same time, the same DSP can perform all of the other control and monitoring functions required by the PFC converter by scheduling processor time slots assigned to various tasks or by interrupt routines.
While DSPs are generally sufficient for PFC converters, they are not optimized for such applications and in practice yield relatively cumbersome and expensive solutions. This is because high quality digital PFC ordinarily requires three high resolution analog to digital conversion channels, at least one of which needs to be high speed. Further, calculation of the proper timing for the main power switch ordinarily requires firmware execution of two relatively complex digital filters optimized for dynamic behavior and stability of the power stage—one for the average current loop and one for the voltage loop. Additionally, several time-critical protection functions, such as overcurrent and overvoltage, must be simultaneously included. All of these functions have to be executed in real time for proper operation of the converter. The existence of multiple time-critical control functions competing for the computing resources of a signal DSP complicates the firmware by introduction of complex scheduling and multilevel interrupt routines. This is turn increases the risk of unintended behavior compromising the operation of the converter. To overcome these challenges, relatively powerful DSPs and complex routines must be used. This makes acceptable DSP implementations prohibitively expensive for low and medium power converters.
Similar challenges have been known in other types of switched mode converters, such as DC/DC point-of-load (POL) converters. One of the ways proposed for DC/DC POL converters to reduce the computational burden of the main processor is to introduce a specialized hardware filter for realizing the main control loop. The coefficients of this filter can be programmed by the main processor to accommodate the dynamic requirements of the converter. This, however, needs to be done only once or perhaps modified only in special situations (abnormal operation, system configuration change, parameters drift, etc).
To reduce further the hardware resources needed for digital pwm controllers, so called “window a/d conversion” has been proposed. In this scheme, the analog-to-digital converter monitoring the output voltage is designed to process only a relatively narrow range of amplitudes around the desired (target) voltage. The insight behind this approach is such that during normal operation the output voltage is very close to the target value. This is because modern electronic systems require very precise voltage regulation and such performance is absolutely necessary for proper operation of the whole system. If the output voltage dwells outside the target window, emergency shut down or other special measures are usually implemented.
Although digital controllers employing window a/d conversion are popular in DC-to-DC converters, such controllers are not suitable for PFC converters. This is because such controllers work only with a single voltage loop, while PFC requires two loops and one of them is an average current mode control loop.